The semiconductor industry has seen tremendous advances in technology that has permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of tens (or even hundreds) of MIPS (millions of instructions per second) to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high-density and high functionality in semiconductor devices has been the demand for multiple layers of metal interconnects for routing signals to and from so many circuit devices, and increased numbers of external electrical connections to be present on the exterior of the die and on the exterior of the semiconductor packages, which receive the die, for connecting the packaged device to external systems such as a printed circuit board.
There have been a number of semiconductor dies and packaging types used to address these issues. Semiconductor devices that have multiple layers of metal signal-routing interconnects are often referred to as multi-layer devices. Multi-layer devices typically have two or more layers (or levels) of metal interconnects built up over the portion of the die having the active devices. At this “circuit” or “front” side of the die, where the transistors and other active circuitry are generally formed, is a very thin epitaxially-grown silicon layer on a single crystal silicon wafer from which the die is singulated. The circuit side of the die is positioned very near the package, and opposes the backside of the die. The substrate between the backside and the circuit side of the die is typically a bulk silicon, such as single crystalline silicon.
To increase the number of pad sites available for a die, especially for multi-layer type dies, various semiconductor packaging types have been developed. One increasingly popular packaging technique is called “controlled collapse chip connection” or “flip-chip” packaging. In this technology, the bonding pads are provided with metal (solder) bumps. The bonding pads need not be on the periphery of the die and hence are moved to the site nearest the transistors and other circuit devices formed in the die. As a result, the electrical path to the pad is shorter. Electrical connection to the package is made when the die is flipped over the package with corresponding bonding pads and soldered. Once a flip-chip die is attached to the package, the backside portion of the die remains exposed. As a result, the dies are often referred to as “flip-chip” devices. Each bump connects to a corresponding package inner lead. The packages that result are lower profile, have lower electrical resistance, and a shortened electrical path.
The output terminals of such packages vary depending on the package type. For example, some output terminals are ball-shaped conductive bump contacts (usually solder, or other similar conductive material), and they are typically disposed in a rectangular array. These packages are occasionally referred to as “Ball Grid Array” (BGA). Another type of package, commonly known as a “Pin Grid Array” (PGA) package, implements the output terminals as pins.
For a flip-chip device with multi-layer metals, accessing the circuitry via the exposed backside of the die can be difficult because the circuit side of the flip-chip die is not visible or accessible for viewing using optical or scanning electron microscopy. The circuitry under the substrate backside of the die is in a very thin layer (e.g., about 10 micrometers) of silicon buried under the bulk silicon (e.g., greater than 500 micrometers).
Although the circuit of the integrated circuit (IC) is buried under the bulk silicon (i.e., the single crystalline silicon), infrared (IR) microscopy is capable of imaging the circuit because silicon is relatively transparent in these wavelengths of the radiation. However, because of the absorption losses of IR radiation in silicon, it is generally required to thin the die to less than about 100 microns in order to view the circuit using IR microscopy. To illustrate this difficulty, on a die that is 725 microns thick, at least 625 microns of silicon must be removed (or thinned) before IR microscopy can be used.
For failure analysis, thinning a flip-chip bonded die to such degrees is time consuming, burdensome, overly complex, and can damage the underlying circuitry that is to be analyzed for potential defects. These issues can be better appreciated through a discussion of the following common approach for such thinning.
Typically, thinning is accomplished by first thinning the die across the whole die surface; this type of thinning is referred to as “global thinning.” Mechanical polishing is one method for global thinning. Once an area is identified as an area of interest and it is determined that access is needed to a particular area of the circuit, local thinning techniques can be used to thin an area smaller than the die size.
Focused ion-beam (FIB) milling is commonly used for thinning the backside of dice to permit e-beam signal acquisition to determine voltage levels of the nodes (e.g., to the millivolt level) while the part is actually operating. FIB milling is effective because it permits for local thinning to expose and/or access target circuitry nondestructively. For flip-chip multi-layer metal devices with advanced processes to expose the lower level metal nodes, the local thinning is implemented by milling deep, narrow holes through the backside of the die. For effective e-beam signal acquisition, the depth of the FIB hole should increase with its width. The ideal aspect ratio (depth to width) of a FIB hole is one to one. For a typical flip-chip having a relatively thick bulk silicon region between the backside and the circuit side of the die, the thickness of FIB holes must have an aspect ratio of about five to one. With this degree of aspect ratio, e-beam signal acquisition is very difficult.
Even when the circuitry is accessible via the type of imaging discussed above, certain defects are not always readily detected. For example, a particular attribute of semiconductor devices that requires testing is the integrity of the device substrate at the substrate surface. During manufacture and processing, the crystalline structure of semiconductor device substrate often becomes damaged. When materials are implanted in the device during operations such as ion implantation, the ions strike the device substrate and lose their energy via electronic and nuclear collisions. If the transferred energy during a nuclear collision is high enough, the atoms are displaced from their lattice sites in the crystalline structure, damaging the substrate. The magnitude of the damage increases as the energy transferred during a collision increases. Damage can also occur during post-processing circuit usage; such damage includes, for example, CMOS latch-up events.
Damaged substrate results in reduced mobility in the damaged regions and defect levels in the band gap of the material, including deep-level traps for both electrons and holes, which have a tendency to capture free carriers from the conduction and valence bands. In addition to damaged crystalline structure, other abnormalities in the semiconductor devices may exist, for example, in the form of impurities in the substrate. If not repaired, the damaged regions may exhibit problems such as high resistivity.
As the semiconductor industry continues to demand increasingly complex and numerous manufacturing processes, the tendency for defects to occur within the substrate increases. Therefore, it would be helpful to have the ability to efficiently test structure within the semiconductor substrate to detect substrate surface damage.